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SV51003
2013.05.06
RAM Blocks Operations
2-15
RAM Blocks Operations
Figure 2-6: Byte Enable Functional Waveform
This figure shows how the wren and byteena signals control the operations of the RAM blocks.
inclock
wren
address
an
a0
a1
a2
a3
a4
a0
data
XXXXXXXX
ABCDEF12
XXXXXXXX
byteena
XXXX
1000
0100
0010
0001
1111
XXXX
contents at a0
contents at a1
contents at a2
contents at a3
contents at a4
FFFFFFFF
FFFFFFFF
FFFFFFFF
FFFFFFFF
FFFFFFFF
ABFFFFFF
FFCDFFFF
FFFFEFFF
FFFFFF12
ABCDEF12
don’t care: q (asynch)
current data: q (asynch)
doutn
doutn
ABXXXXXX
ABFFFFFF
XXCDXXXX
FFCDFFFF
XXXXEFXX
FFFFEFFF
XXXXXX12
FFFFFF12
ABCDEF12
ABCDEF12
ABFFFFFF
ABFFFFFF
Memory Blocks Packed Mode Support
The M20K memory blocks support packed mode.
The packed mode feature packs two independent single-port RAM blocks into one memory block. The
Quartus II software automatically implements packed mode where appropriate by placing the physical RAM
block in true dual-port mode and using the MSB of the address to distinguish between the two logical RAM
blocks. The size of each independent single-port RAM must not exceed half of the target block size.
Memory Blocks Address Clock Enable Support
The embedded memory blocks support address clock enable, which holds the previous address value for as
long as the signal is enabled ( addressstall = 1 ). When the memory blocks are configured in dual-port
mode, each port has its own independent address clock enable. The default value for the address clock enable
signal is low (disabled).
Embedded Memory Blocks in Stratix V Devices
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